1. Field of the Invention
This invention relates generally to chemical mechanical planarization, and more particularly to a carrier head having location optimized vacuum holes for reducing non-uniformity film effect during a chemical mechanical planarization process.
2. Description of the Related Art
In the fabrication of semiconductor devices, planarization operations are often performed, which can include polishing, buffing, and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide.
As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal planarization operations are performed to remove excess metallization. Further applications include planarization of dielectric films deposited prior to the metallization process, such as dielectrics used for shallow trench isolation or for poly-metal insulation. One method for achieving semiconductor wafer planarization is the chemical mechanical planarization (CMP) process.
In general, the CMP process involves holding and rubbing a typically rotating wafer against a moving polishing pad under a controlled pressure and relative speed. CMP systems typically implement orbital, belt, or brush stations in which pads or brushes are used to scrub, buff, and polish one or both sides of a wafer. Slurry is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
An effective CMP process has a high polishing rate and generates a substrate surface which is both finished, that is, lacks small-scale roughness, and flat, meaning that the surface lacks large-scale topography. The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad.
The polishing rate depends upon the force pressing the substrate against the pad. Specifically, the greater this force, the higher the polishing rate. If the carrier head applies a non-uniform load, i.e., if the carrier head applies less force to one region of the substrate than to another, then the low pressure regions will be polished slower than the high pressure regions. Therefore, a non-uniform load may result in non-uniform polishing of the substrate.
FIG. 1 is an illustration showing a conventional carrier head 100, which includes a stainless steel plate 104 surrounded by a retaining ring 102 for holding a wafer in position during polishing. Typically, a carrier film (not shown) positioned within the retaining ring 102 covers the stainless steel plate 104. In addition, vacuum holes 106 are positioned in the stainless steel plate 104 at a particular distance D108, typically about 14.3 millimeters (mm) in the conventional carrier head 100, from the edge of the stainless steel plate 104.
The carrier film is designed to absorb pressure during wafer polishing, thus preventing hot pressure spots from occurring on the wafer surface. In the present disclosure, the term xe2x80x9chot pressure spotsxe2x80x9d refers to wafer surface areas wherein increased downforce pressure results in a higher removal rate for that wafer surface area. Thus, hot pressure spots can result in non-uniformity problems during CMP processing, which are generally avoided by the use of the carrier film.
During wafer processing, the wafer must be transported from station to station. To facilitate wafer transportation, the carrier head 100 includes vacuum holes 106 that allow the carrier head 100 to pick up and drop off the wafer. For example, after completing a polishing operation, the carrier head 100 transports the wafer from the surface of the polishing belt to the next station in the wafer fabrication process. However, the wafer often experiences xe2x80x9cstictionxe2x80x9d with the polishing belt. That is, the combination of the polyurethane of the polishing belt surface and the slurry often causes the wafer to adhere to the surface of the polishing belt. To break this adhesion, the carrier head 100 applies a vacuum to the back of the wafer via the vacuum holes 106, which allows the carrier head 100 to lift the wafer from the surface of the polishing belt. After transporting the wafer to the next wafer fabrication station, the carrier head 100 applies a positive airflow through the vacuum holes 106 to release the wafer from the carrier film of the carrier head 100.
Unfortunately, the vacuum holes 106 of the carrier head 100 cause low removal rate areas on the surface of the wafer, which result in non-uniformity errors. FIG. 2 is a diagram showing an exemplary wafer 200 resulting from CMP operations using the conventional carrier head of FIG. 1. During the CMP process the carrier film on the carrier head is wet. However, when vacuum is applied through the carrier head vacuum holes, the vacuum tends to dry out the carrier film around the vacuum holes, which can make the carrier film softer in the regions of the vacuum holes. In addition, there is no direct wafer support in the regions of the vacuum holes. Thus, because of the dry carrier film and lack of wafer support in the region of the vacuum holes, the low removal rate xe2x80x9cvacuum holexe2x80x9d regions 202 occur on the surface of the wafer 200. The resulting non-uniformity can have a dramatic negative affect on the devices formed on the wafer, often causing the effected dice at this area to be discarded.
Carrier heads have been developed that attempt to avoid low removal rate vacuum hole regions on the surface of the wafer. For example, one conventional carrier head uses an inflatable bladder essentially in place of the stainless steel plate to transfer downforce to the back of the wafer during the CMP process. However, this inflatable bladder requires a floating retaining ring that complicates the CMP process. Moreover, the floating retaining ring generally causes undesirable edge effects, wherein the removal rate at the edge of the wafer is very high with respect to the remainder of the wafer.
In view of the foregoing, there is a need for a carrier head that avoids low removal rate vacuum hole regions on the surface of the wafer. The carrier head should be usable on various types of CMP systems, and should not require undue experimentation and engineering to implement. In particular, the carrier head should not require overly complex systems, such as a floating retaining ring, and should provide a uniform wafer surface during CMP.
Broadly speaking, the present invention fills these needs by providing a carrier head having location optimized vacuum holes for improved uniformity during CMP operations. Generally, embodiments of the present invention relocate the vacuum holes of the carrier head to within the edge exclusion zone of the wafer. In one embodiment, a carrier head for use in a CMP process is disclosed. The carrier head includes a metal plate that is capable of transferring a downforce to a wafer during a CMP operation. A plurality of vacuum holes is disposed within the metal plate, wherein each vacuum hole is positioned such that the vacuum hole is within five millimeters of an edge of the wafer during the CMP operation. In this manner, each vacuum hole can be positioned such that the vacuum hole is within an edge exclusion zone of the wafer during the CW operation. In some embodiments, each vacuum hole is positioned such that the vacuum hole is within three millimeters of the edge of the wafer during the CMP operation, such as 2.7 millimeters from the edge of the wafer.
A method for making a carrier head for use in a CMP process is disclosed in a further embodiment of the present invention. The method includes providing a metal plate that is capable of transferring a downforce to a wafer during a CMP operation, and boring a plurality of substantially horizontal air channels from the edge of the metal plate toward the center of the metal plate. In addition, a plurality of air ports are drilled into the metal plate. Each air port is located within five millimeters of the edge of the metal plate and is connected to an air channel. Further, the axis of each air port forms an angle greater than 90xc2x0 toward the center of the metal plate and relative to a plane that is parallel to the surface of the metal plate and in a plane substantially perpendicular to the surface of the metal plate. In this manner, an end of each air port forms a vacuum hole in the surface of the metal plate. Generally, an end of each horizontal air channel present at the edge of the metal plate is plugged. Further, each air port generally is capable of providing air pressure toward the center of the wafer to release the wafer from the carrier head.
An additional carrier head for use in a CMP process is disclosed in a further embodiment of the present invention. As above, the carrier head includes a metal plate capable of transferring a downforce to a wafer during a CMP operation. Further, a plurality of substantially horizontal air channels extend from the edge of the metal plate toward a center of the metal plate. Also, a plurality of vacuum holes are disposed within the metal plate and are connected to the plurality of air channels via air ports. As above, an axis of each air port forms an angle greater than 90xc2x0 relative to a plane that is parallel to a surface of the wafer toward a center of the wafer. In addition, each vacuum hole is positioned such that the vacuum hole is within an edge exclusion zone of the wafer during the CMP operation.
Embodiments of the present invention can be advantageously utilized to polish wafers without generating low removal rate vacuum hole regions of the wafer surface. In particular, each vacuum hole is positioned within the edge exclusion zone of the wafer during the CMP operation. Because devices are not fabricated in this area of the wafer, removal rates are much less important within the edge exclusion of the wafer.
Further, the edge of a wafer is much more ridged than the center areas of the wafer. Thus, the physics of the wafer itself make points on the edge of the wafer much stiffer than points located more centrally on the wafer. As a result, the vacuum holes have much less affect on the wafer removal rate when located within 3 millimeters of the wafer""s edge, such as when located at 2.7 millimeters from the edge of the wafer. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.